1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a method for fabricating a CMOS-TFT array substrate by a low-mask technology.
2. Discussion of the Related Art
Recently, liquid crystal display (LCD) devices are widely used for flat displays because of their high contrast ratio, great gray scale and image display, and low power consumption.
In operation, the LCD device includes various patterns such as driving devices or lines on a substrate, which may be formed by photolithography. For example, a photoresist sensitive ultraviolet rays is coated on the substrate and a pattern formed using an optical mask is exposed and developed on the photoresist. Then, various material layers are etched using the patterned photoresist as a mask, and the photoresist is stripped. Accordingly, research for reducing the number of masks required has been actively pursued to improve productivity by decreasing the number of photolithography process.
Typically, the LCD device includes a TFT array substrate, a color filter substrate, a liquid crystal layer, and a driving circuit. At this time, the TFT array substrate includes a thin film transistor TFT for selectively applying signals to pixel electrodes, and a storage capacitor for maintaining a charging state until a unit pixel region is addressed to the next charging state. Also, the color filter substrate has a color filter layer for obtaining various colors. Also, the liquid crystal layer is formed between the two substrates, and the driving circuit causes images to be displayed according to external signals by driving the TFT array substrate.
In case of a transflective type LCD device, the unit pixel region is divided into a transmitting part and a reflective part. At this time, a transmitting electrode is formed in the transmitting part, and a reflective electrode is formed in the reflective part, whereby a constant voltage is applied to the liquid crystal layer.
The transmitting part displays the images by providing the light emitted from a backlight and incident on a lower substrate to the liquid crystal layer. Meanwhile, the reflective part displays the images by reflecting the ambient light incident on an upper substrate. Then, the driving circuit is provided on an additional PCB substrate, and is connected with the TFT array substrate by TCP. However, a method of forming the TFT array substrate without forming the driving circuit on the additional PCB substrate has been proposed recently.
Also, the thin film transistor is categorized into a thin film transistor for a pixel to drive the pixel regions in an active area, and a thin film transistor for a driving circuit to apply signals to gate and data lines in a pad area by operating the thin film transistor for a pixel. Typically, the thin film transistor for a pixel is formed of an n-type TFT of a high speed operation, and the thin film transistor for a driving circuit is formed of a CMOS (complementary metal-oxide semiconductor) thin film transistor, wherein the CMOS thin film transistor is comprised of the n-type TFT and a p-type TFT having a low power consumption.
Hereinafter, a method for fabricating a related art transflective type LCD device having a CMOS-TFT will be described with reference to the accompanying drawings.
First, as illustrated in FIG. 1A, a buffer layer 52 is formed on an insulating substrate 11, and a polysilicon layer is formed on the buffer layer 52. Then, a first photoresist (not shown) is deposited on the polysilicon layer, and first, second, and third semiconductor layers 54a, 54b, and 54c are formed by photolithography using a first mask.
There are at least two methods for forming the polysilicon layer: a first method of directly depositing a polysilicon layer and a second method of depositing an amorphous silicon layer and crystallizing the deposited amorphous silicon layer to a polysilicon layer.
The first method includes an LPCVD (low pressure chemical vapor deposition) method, and a PECVD (plasma enhanced chemical vapor deposition) method. In the LPCVD method, the polysilicon layer is deposited at a high temperature above 550° C. In case of the PECVD method, the polysilicon layer is deposited at a temperature below 400° C. by using a mixing gas of SiF4/SiH4/H2.
The second method includes an SPC (solid phase crystallization) method of performing a heat treatment at a high temperature for a long time, an ELA (eximer laser annealing) method of irradiating an eximer laser at a temperature of 250° C., and an MIC (metal induced crystallization) method of inducing crystallization by depositing a metal layer on the amorphous silicon layer.
The semiconductor layers 54a, 54b, and 54c are patterned in an island shape. At this time, n-type TFT and p-type TFT regions are respectively formed in the first and third semiconductor layers 54a and 54c, and a storage capacitor is formed in the second semiconductor layer 54b. 
Next, as illustrated in FIG. 1B, a second photoresist 31 is coated on an entire surface of the insulating substrate 11, and an exposure and developing process is performed thereon, so that the second photoresist 31 is patterned to cover the first semiconductor layer 54a of the n-type TFT region, and the third semiconductor layer 54c of the p-type TFT region. After that, by performing a storage doping process to the entire surface of the substrate, a storage doping layer is formed in the second semiconductor layer 54b of a storage region.
Subsequently, as illustrated in FIG. 1C, after removing the second photoresist 31, an inorganic insulating layer of silicon oxide SiOx or silicon nitride SiNx is deposited on the entire surface of the insulating substrate 11, by PECVD (plasma enhanced chemical vapor deposition), thereby forming a gate insulating layer 13. Thereafter, a low-resistance metal layer, for example, copper Cu, aluminum Al, aluminum molybdenum AlNd, molybdenum Mo, chrome Cr, titanium Ti, tantalum Ta, or molybdenum-tungsten MoW, is deposited on the gate insulating layer 13. Then, after a third photoresist (not shown) is deposited on the low-resistance metal layer, first and second gate electrodes 12 and 22 and a storage electrode 19 are formed in the respective semiconductor layers 54a, 54b, and 54c by photolithography using a third mask. In this state, the first and second gate electrodes 12 and 22 are partially overlapped with first and second channel layers 14 and 24 of the n-type TFT region and the p-type TFT region, and the storage electrode 19 is overlapped with the second semiconductor layer 54b of the storage region.
Next, n-type impurity ions are lightly doped on the semiconductor layers 54a and 54c by using the first and second gate electrodes 12 and 22 as a mask, thereby forming LDD (lightly doped drain) doping layers 88 in the semiconductor layer 54a and 54c at both sides of the first and second gate electrodes 12 and 22. At this time, the remaining portions of the first and second semiconductor layers 54a and 54c, on which the n-type impurity ions are not doped, serve as the first and second channel layers 14 and 24.
As described above, the LDD doping layer is formed by lightly doping the predetermined portions of the semiconductor layer with the impurity ions, whereby it is possible to decrease a turning-off current by decreasing an electric field of a contact region by resistance, and to minimize the decrease of a turning-on current.
After that, as illustrated in FIG. 1D, a fourth photoresist 33 is coated on the entire surface of the substrate including the first gate electrode 12, and then an exposure and developing process using a fourth mask is performed thereon, whereby the fourth photoresist 33 is patterned to expose some of the first semiconductor layer 54 corresponding to the n-type TFT region at both sides of the first gate electrode 12. Accordingly, the p-type TFT region and the storage region are blocked, so that it is possible to prevent the ions from being implanted to the p-type TFT region and the storage region.
Then, the entire surface of the insulating substrate 11 is highly doped with the n-type impurity ions of phosphorous P, thereby forming first source and drain regions 15a and 15b in the n-type TFT region. After that, the first source and drain regions 15a and 15b are activated. After stripping the fourth photoresist 33, as illustrated in FIG. 1E, a fifth photoresist 35 is coated on the entire surface of the substrate including the first and second gate electrodes 12 and 22, and then patterned to expose the p-type TFT region by an exposure and developing process using a fifth mask. As a result, the n-type TFT region and the storage region are blocked, whereby the ions are not implanted thereto.
Subsequently, the p-type impurity ions, such as-boron B, are highly doped on the entire surface of the insulating substrate 11, thereby forming second source and drain regions 25a and 25b in the p-type TFT region. Then, the second source and drain regions 25a and 25b are activated. After stripping the fifth photoresist 35, as illustrated in FIG. 1F, an insulating material such as silicon oxide or silicon nitride is deposited on the entire surface of the substrate including the first gate electrode 12, by PECVD, thereby forming an insulating interlayer 23.
Thereafter, a sixth photoresist (not shown) is coated, and the gate insulating layer 13 and the insulating interlayer 23 are selectively removed to expose predetermined portions of the first and second source/drain regions 15a, 15b, 25a, and 25b by photolithography using a sixth mask, thereby forming a first contact hole 71.
By stripping the sixth photoresist, as illustrated in FIG. 1G, first and second source/drain electrodes 15c, 15d, 25c, and 25d are connected with the first and second source/drain regions 15a, 15b, 25a, and 25b through the first contact hole 71, thereby completing the CMOS-TFT having the n-type TFT and the p-type TFT.
That is, a low-resistance metal layer such as copper Cu, aluminum Al, aluminum neodymium AlNd, molybdenum Mo, chrome Cr, titanium Ti, tantalum Ta, or molybdenum-tungsten MoW, and a seventh photoresist (not shown) are sequentially coated on the entire surface of the substrate including the insulating interlayer 23, to bury the first contact hole 71. Then, the coated low-resistance metal layer is patterned in an exposure and developing process using a seventh mask, thereby forming the first and second source/drain electrodes 15c, 15d, 25c, and 25d. 
Accordingly, the n-type TFT is formed in each pixel region to drive the pixel region, wherein the n-type TFT is comprised of the first gate electrode 12, the first source/drain electrodes 15c and 15d, and the first channel layer 14. Also, the p-type TFT is formed in the driving circuit, to apply the signals to the gate and data lines, wherein the p-type TFT is comprised of the second gate electrode 22, the second source/drain electrodes 25c and 25d, and the second channel layer 24. Also, the storage including the second semiconductor layer 54b, the gate insulating layer 13, and the storage electrode 19 is formed in each pixel region.
As illustrated in FIG. 1H, after stripping the seventh photoresist, a photoacryl resin is coated on the entire surface of the substrate including the first source/drain electrodes 15c and 15d, and then an exposure and developing process using an eighth mask is performed thereon, thereby forming a plurality of photoacryl resin patterns at fixed intervals. Then, by reflowing the plurality of photoacryl resin patterns, it is possible to form a plurality of first projection patterns 90. Thus, the plurality of first projection patterns 90 are formed at fixed intervals, wherein each first projection pattern is formed in a spherical shape.
Subsequently, as illustrated in FIG. 1I, an inorganic insulating layer of silicon oxide SiOx or silicon nitride SiNx is deposited on the entire surface of the substrate including the first projection patterns 90, or an organic insulating layer of BCB (BenzoCycloButene) or acrylic material is coated on the entire surface of the substrate, thereby forming a passivation layer 16. At this time, the passivation layer 16 is formed along the first projection patterns 90, whereby the passivation layer 16 has a plurality of second projection patterns 92.
Referring to FIG. 1J, the passivation layer 16 and the insulating interlayer 23 are etched to expose the first drain electrode 15d and the storage electrode 19 by photolithography using a ninth mask, thereby forming a second contact hole 81.
Subsequently, as illustrated in FIG. 1K, a metal layer having high reflexibility, for example, aluminum-Al, aluminum neodymium AlNd, or titanium Ti, is deposited on the entire surface of the substrate including the passivation layer 16, and patterned by photolithography using a tenth mask, thereby forming a reflective electrode 17a. The reflective electrode 17a is formed along the second projection patterns 92, whereby the reflective electrode 17a has reflective projections. If the ambient light is used as the light source, the reflective projections partially changes reflection angle of the ambient light, thereby obtaining a great amount of reflective light.
As illustrated in FIG. 1L, ITO (indium-tin-oxide) or IZO (indium-zinc-oxide) is deposited on the entire surface of the substrate including the reflective electrode 17a, and then patterned by photolithography using an eleventh mask, thereby forming a transmitting electrode 17b. At this time, the reflective electrode 17a is formed in the reflective part of the pixel region, and the transmitting electrode 17b is formed in the transmitting part of the pixel region. However, the transmitting electrode 17b is in contact with the predetermined portion of the reflective electrode 17a, to receive the voltage.
Accordingly, the related art fabrication process of the TFT array substrate totally uses a mask eleven times.
Although not shown, the CMOS-TFT array substrate having the n-type TFT and the p-type TFT is maintained at a predetermined interval from a facing substrate having a color filter layer by spacers, and then the two substrates are bonded to each other by sealant. Then, a liquid crystal layer is formed by injecting liquid crystal between the two substrates, and an inlet for injection of liquid crystal is sealed, thereby completing the LCD device.